Connection between OMAP and slave (here DM9000)
The DM9000 has the following pins that needs to be connected in order to make it work.
(Only communication is discused, it also needs a clk and powersupply)
- CS - ChipSelect
- nOE - OutputEnable, active low (n)
- nWE - WriteEnable, active low
- CMD - Command Type, determines if access is as a data- or indexport
- D[0:15] - 16 bit databus
The OMAP has:
- 8 chipselects
- OE
- WE
- GPMC_A[1:10] - 10 bit address bus
- GPMC_D[0:15] - 16 bit data bus
The below figure shows how the General Purpose Memory Control on the OMAP can be connected to the DM9000 Ethernet controller.
Relevant timing diagrams
Read timing diagram:
Read timing table
Write timing diagram:
Write timing table
Determining constants for registers bases on timing diagrams
Read-Cycle:
- CSONTIME = 0ns
- Determines when
chipselect can go ON
- DM9000 doesn’t care in
which order CS og CMD comes
- Configured in
GMPC_CONFIG2_i [3:0]
- OEONTIME
= 10ns
- Gives the slave
permission to start sending.
- T1 = 0ns and the least
we can give is 10ns
- Configured in GMPC_CONFIG4_i
[3:0]
- OEOFFTIME
= T1 (OEONTIME) + T2 = 10ns + 20ns = 30ns
- Terminates slaves
permission to send. OEOFFTIME – OEONTIME = IOR# on DM9000
- T2 = 10ns as a minimum,
so has to be 20ns for us to be sure
- Configured in GMPC_CONFIG4_i
[12:8]
- CSRDOFFTIME = T1 (OEONTIME) + T2 + T5 =
10ns + 20ns + 10ns = 40ns
- Terminates chip select.
Same as end of CS#,CMD on DM9000
- T2 = 10ns becomes 20ns
as before
- T5 = 0ns so have to make
it 10ns to be surten
- Configured in GMPC_CONFIG2_i
[12:8]
- RDACCESSTIME
= T1 + T3 = 10ns + 10ns = 20ns
- Determines when it’s
safe to read data on DM9000.
- T3 = 3ns, indicates that
3ns after IOR# is ON the data is ready for reading.
- Configured in GMPC_CONFIG5_i
[20:16]
- RDCYCLETIME = T1 + T2 + T5 = 10ns + 20ns +
10ns = 40ns
- Indicates how much times
it takes to complete one read-cycle
- Configured in GMPC_CONFIG5_i
[4:0]
- CYCLE2CYCLEDELAY = T6 - T5 - T1 = 80ns - 10ns – 10ns = 60ns
- Indicates when you can
start the next read, ie. IOR# OFF to IOR# ON again.
- T6 is given as 2 and 4
cycles of 20ns (DM9000 has a different clock). We have to take whichever
is higher.
- Note that this is configured
in the same directory with the same bits as the write cycle. Therefore
always select the longest time.
- Configured in GMPC_CONFIG6_i
[11:8]
Write-Cycle:
- WEONTIME
= T1 = 10ns
- T1 = 0ns, so have to
round up to be sure the chip is selected before IOW# is set ON
- Configured in GMPC_CONFIG4_i
[19:16]
- WEOFFTIME =
T1 + T2 = 10ns + 20ns = 30ns
- T2 = 10ns, indicates how
long the IOW# has to be ON to write. We have to round up.
- Configured in GMPC_CONFIG4_i
[28:24]
- CSWROFFTIME = T1 + T2 + T5 = 10ns + 20ns +
10ns = 40ns
- Configured in GMPC_CONFIG2_i
[20:16]
- WRCYCLETIME = T1 + T2 + T5 = 10ns + 20ns +
10ns = 40ns
- Configured in GMPC_CONFIG5_i
[12:8]
- CYCLE2CYCLEDELAY = T6 - T5 - T1 = 40ns -
10ns - 10ns = 20ns
- Configured in GMPC_CONFIG6_i
[11:8]
Documents of interrest
- DevKit8000 schematic
- http://devkit8000.wikispaces.com/
- For an example of an actual application
- Spruf98c - OMAP35c Applications Processor, technical reference manual
- Timing diagram, pp. 1147 and 1149
- DM9000A - datasheet
- Timing diagram, pp. 49 and 50
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